During fabrication of very large scale integrated (VLSI) circuit die on a semiconductor wafer, it is desirable to include a one-time programmable (OTP) nonvolatile memory element which can be programmed either during wafer probe or after packaging the die. For example, programming of a OTP nonvolatile memory element is used to provide self-contained identification information about an individual integrated circuit die or die revision. OTP nonvolatile memory is also used for remapping defective dynamic random access memory (DRAM) cell addresses so that functional redundant cells are addressed instead. OTP nonvolatile memory also provides hard-coded digital trimming data for precision analog elements such as bandgap voltage references or other numerous applications where non-volatile data storage is desirable.
There are several ways to implement nonvolatile storage on an integrated circuit die. In one method, fusible links are fabricated in the die. Data is represented in the fusible links by using a laser to selectively trim them, creating open circuits in the fusible links. Laser trimming is difficult and time consuming, involving precise control of the power and position of the focused energy. It is more convenient to electrically program nonvolatile memory during wafer probe without using a laser. Metal fuses exist which can be selectively electrically programmed by exceeding a certain current and thereby creating an open circuit in the fuse.
Antifuses have also been used. They are selectively electrically programmed by applying a programming voltage to break down a dielectric material contacted by two conductive terminals of the antifuse. This permanently changes the resistance presented by the antifuse from a high initial resistance to a low programmed resistance. The programmed resistances typically obtained are on the order of several thousand ohms. In accessing the antifuse for a read operation, the programmed resistance is used, for example, to couple the input capacitance of a logic gate to a high logic level provided by a power supply, or to a low logic level provided by a connection to ground. The time required to charge or discharge the input capacitance of a logic gate is proportional to the product of the programmed resistance of the fuse and the input capacitance of the logic gate. It is desirable to obtain an even lower value of programmed resistance in order to decrease the read access time.
The required programming voltage of an antifuse is quite high, around 11 to 12 volts, and this high programming voltage must be routed to the selected antifuse using other circuits on the integrated circuit chip. Except for routing these high antifuse programming voltages, the other circuits on the integrated circuit chip typically need not be capable of withstanding these high voltages and resulting high electric fields. The introduction of high antifuse programming voltages may require design and process modifications such as tailored junction doping profiles or thick gate oxides in order to avoid damage to the integrated circuit die. Thus, it is desirable to reduce the voltage required for programming a memory element in order to reduce the design constraints on the routing circuits.
Implementation of both fuses and antifuses adds new considerations to an existing integrated circuit process. It is desired to implement a nonvolatile memory element without adding new considerations or complexity to an existing very large scale integrated (VLSI) circuit process.